1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to various methods for determining, tracking and/or controlling processing based upon various characteristics of silicon wafers.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
By way of background, an illustrative field effect transistor 10, as shown in FIG. 1, may be formed above a surface 15 of a semiconducting substrate or wafer 11 comprised of doped-silicon. The substrate 11 may be doped with either N-type or P-type dopant materials. The transistor 10 may have a doped polycrystalline silicon (polysilicon) gate electrode 14 formed above a gate insulation layer 16. The gate electrode 14 and the gate insulation layer 16 may be separated from doped source/drain regions 22 of the transistor 10 by a dielectric sidewall spacer 20. The source/drain regions 22 for the transistor 10 may be formed by performing one or more ion implantation processes to introduce dopant atoms, e.g., arsenic or phosphorous for NMOS devices, boron for PMOS devices, into the substrate 11. Shallow trench isolation regions 18 may be provided to isolate the transistor 10 electrically from neighboring semiconductor devices, such as other transistors (not shown). Additionally, although not depicted in FIG. 1, a typical integrated circuit device is comprised of a plurality of conductive interconnections, such as conductive lines and conductive contacts or vias, positioned in multiple layers of insulating material formed above the substrate. These conductive interconnections allow electrical signals to propagate between the transistors formed above the substrate 11.
In the process of forming integrated circuit devices, millions of transistors, such as the illustrative transistor 10 depicted in FIG. 1, are formed above a semiconducting substrate. In general, semiconductor manufacturing operations involve, among other things, the formation of layers of various materials, e.g., polysilicon, insulating materials, metals, etc., and the selective removal of portions of those layers by performing known photolithographic and etching techniques. These processes, along with various ion implant and heating processes, are continued until such time as the integrated circuit device is complete.
During the course of fabricating such integrated circuit devices, a variety of features, e.g., gate electrodes, conductive lines, openings in layers of insulating material, etc., are formed to very precisely controlled dimensions. Such dimensions are sometimes referred to as the critical dimension (CD) of the feature. It is very important in modem semiconductor processing that features be formed as accurately as possible due to the reduced size of those features in such modern devices. For example, gate electrodes may now be patterned to a width 12 that is approximately 0.18 xcexcm (1800 xc3x85), and further reductions are planned in the future. The width 12 of the gate electrode 14 corresponds approximately to the channel length 13 of the transistor 10 when it is operational. Thus, even slight variations in the actual dimension of a feature as fabricated may adversely affect device performance.
FIG. 2 depicts an illustrative embodiment of a wafer 11 having a plurality of die 24 formed thereabove. The die 24 define the area of the wafer 11 where production integrated circuit devices, e.g., microprocessors, ASICs, memory devices, will be formed. The size, shape and number of die 24 per wafer 11 depend upon the type of device under construction. For example, several hundred die 24 may be formed above an 8-inch diameter wafer 11. The die 24 are separated by scribe lines 26. Eventually, after all processing operations are complete, the wafer 11 will be cut along the scribe lines 26, and each of the production die 24 will be packaged and sold.
In modern semiconductor manufacturing, great care is taken in producing the wafers 11 upon which various integrated circuit devices will be formed. In fact, a purchaser of such wafers from a wafer vendor will often provide a very detailed wafer product specification to the vendor that sets forth various required characteristics of the wafers to be purchased. Such wafers may be comprised of a variety of materials, e.g., silicon, gallium arsenide, etc., and they may be formed by a variety of techniques. For example, silicon wafers are typically formed by initially forming a cylindrically shaped ingot of the material, and, thereafter, slicing or sawing the ingot into individual wafers 11. In some cases, a layer of epitaxial silicon (not shown) may be formed on one surface of the wafer by the wafer manufacturer. The silicon material is often doped with an N-type or P-type dopant material.
There are many known processes for forming such ingots of material, e.g., the Czochralski method, the float zone method, the liquid crystal-encapsulated (LEC) Czochralski method (for gallium arsenide), etc. In general, the manufacture of integrated circuit devices require extremely tight product specifications for the wafers, and a high degree of crystal perfection. However, even with the most sophisticated techniques, defects or imperfections still occur, to some degree, in the wafers used in manufacturing integrated circuit devices. Such imperfections include, but are not limited to, crystalline defects, e.g., point defects, dislocations and growth defects, doping level defects, surface flatness or irregularities, resistivity variations, variations in the thickness of the epitaxial silicon layer, etc. Such defects may cause undesirable current leakages, or other electrical performance deficiencies, in completed devices. Obviously, such problems are undesirable in modern semiconductor device manufacturing.
The present invention is directed to a method and system that may solve, or at least reduce, some or all of the aforementioned problems.
The present invention is generally directed to various methods for determining, tracking and/or controlling processing based upon wafer characteristics. In one illustrative embodiment, the method comprises providing a group of wafers, each wafer having a plurality of wafer characteristics, determining a semiconductor device type to be manufactured, selecting a plurality of wafers from the group of wafers based upon the semiconductor device type to be manufactured and at least one of the wafer characteristics and manufacturing a plurality of the determined semiconductor devices on the selected plurality of wafers. In another embodiment, the method comprises providing the wafer characteristics and the identified semiconductor device type to a controller that selects a plurality of wafers from the group of wafers based upon one or more of the wafer characteristics and the type of semiconductor device to be manufactured.
In another illustrative embodiment, the method comprises providing a group of wafers, each wafer having an identification mark, performing a plurality of process operations on each of the wafers to form integrated circuit devices thereabove and performing at least one metrology test at some point after the process operations have been performed, to produce device metrology data. The method further comprises identifying wafers wherein the device metrology data lies outside of a preselected acceptable range and identifying a source of the wafers wherein the device metrology data lies outside of the preselected range based upon the wafer identification mark. In some cases, the wafer identification mark and device metrology data may be provided to a controller and the controller may identify the source of wafers when the device metrology data lies outside of the preselected acceptable range.
In yet another illustrative embodiment, the method comprises providing a plurality of wafers, the wafers having an identification mark and a plurality of wafer characteristics, storing the wafer identification marks and wafer characteristics associated with the marks in a database and providing at least one of the wafers to a processing tool. The method further comprises accessing the database to determine at least one of the wafer characteristics of at least one wafer provided to the processing tool and determining at least one parameter of a process operation to be performed on the wafer in the processing tool based upon the determined wafer characteristic of the wafer.